Embodiments of the inventive concept relate generally to semiconductor memory devices. More particularly, embodiments of the inventive concept relate to phase change memory devices and systems, and related programming methods.
Phase change memory devices store data using phase change materials, such as chalcogenide, which are capable of stably transitioning between amorphous and crystalline phases. The amorphous and crystalline phases (or states) exhibit different resistance values, which are used to distinguish different logic states of memory cells in the memory devices. In particular, the amorphous phase exhibits a relatively high resistance, and the crystalline phase exhibits a relatively low resistance.
Phase change memory devices typically use the amorphous state to represent a logical “1” and the crystalline state to represent a logical “0”. The crystalline state is generally referred to as a “set state”, and the amorphous state is referred to as a “reset state”. Accordingly, phase change memory cells in the phase change memory devices typically store a logical “0” (“SET data”) by “setting” a phase change material in the memory cells to the crystalline state, and the phase change memory cells store a logical “1” (“RESET data”) by “resetting” the phase change material to the amorphous state. A phase change memory cell having the “reset state” can be said to store “RESET data” and a phase change memory cell having the “set state” can be said to store “SET data”. Various phase change memory devices are disclosed, for example, U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase change material in a phase change memory device is typically converted to the amorphous state by heating the material to above a predetermined melting temperature and then quickly cooling the material. The phase change material is typically converted to the crystalline state by heating the material at another predetermined temperature below the melting temperature for a period of time. Accordingly, data is written to memory cells in a phase change memory device by converting the phase change material in memory cells of the phase change memory device between the amorphous and crystalline states using heating and cooling as described.
The phase change material in a phase change memory device typically comprises a compound including germanium (Ge), antimony (Sb), and tellurium (Te), i.e., a “GST” compound. The GST compound is well suited for a phase change memory device because it can quickly transition between the amorphous and crystalline states by heating and cooling.
At least one type of phase change memory cell comprises a top electrode, a chalcogenide layer, a bottom electrode contact, a bottom electrode, and an access transistor or a diode, wherein the chalcogenide layer is the phase change material of the phase change memory cell. Accordingly, a read operation is performed on the phase change memory cell by measuring the resistance of the chalcogenide layer, and a program operation is performed on the phase change memory cell by heating and cooling the chalcogenide layer as described above. A phase change memory cell typically further comprises a switching element used to control a supply of current to the phase change material for program operations.
FIG. 1 is a schematic block diagram and a circuit diagram illustrating one type of conventional phase change memory cell. The phase change memory cell of FIG. 1 comprises a resistor and a switching element (shown by circuit symbols in a broken oval). The resistor comprises a phase change layer 1, an upper electrode 2 formed above phase change layer 1, and a lower electrode 3 formed below phase change layer 1. In the example of FIG. 1, phase change layer 1 comprises the phase change material for the phase change memory cell.
As described above, the phase of the phase change material can be transformed by temperature changes. For example, the phase change memory cell of FIG. 1 can be programmed by closing the switching element to supply a current to the resistor. When the current is supplied to the resistor, lower electrode 3 heats up, causing phase change layer 1 to heat up.
Accordingly, as described above, the phase change memory cell of FIG. 1 can be programmed to the amorphous, or “reset” state by heating phase change layer 1 to a temperature T1 using lower electrode 3 and then quickly cooling phase change layer 1. Similarly, the phase change memory cell of FIG. 1 can be programmed to the crystalline, or “set” state by heating phase change layer 1 to a second temperature T2 (T2<T1) and maintaining phase change layer 1 at temperature T2 using lower electrode 3, and then and then cooling phase change layer 1. In one example, T1 is roughly equal to 1 ns and T2 is around 30-50 ns.
As an example, FIG. 2 is a graph illustrating a temperature profile of a phase change memory cell during a program operation. As seen in FIG. 2, the phase change memory cell is programmed to the reset state by applying a current “i1” to the phase change memory cell for a first time period to heat the phase change material within the phase change memory cell to above temperature T1. After the phase change material reaches temperature T1, current “i1” is no longer applied to the phase change memory cell and the phase change material rapidly cools.
The phase change memory cell is programmed to the set state by applying a current “i2” to the phase change memory cell for a second time period longer than the first time period. Current “i2” heats the phase change material to above temperature T2 and maintains the phase change material above temperature T2 throughout the second time period. Then, after the second time period, current “i2” is no longer applied to the phase change memory cell, allowing the phase change material to cool.
An amount of heat “J” applied to phase change layer 1 is proportional to I2R, where “I” denotes a magnitude of a current “I” flowing through lower electrode 3, and “R” denotes a resistance “R” of lower electrode 3. Resistance “R” is proportional to a cross-sectional area of lower electrode 3, and the cross-sectional area of lower electrode 3 is proportional to πr2, where “r” denotes a radius “r” of lower electrode 3. Therefore, heat “J” applied to phase change layer 1 is generated in proportion to the square of the radius of lower electrode 3. In other words, heat “J” is proportional to r2.
The lower electrodes of different phase change memory cells in a phase change memory device tend to have slightly different radii due to minor variations in processes used to form the phase change memory cells. As a result, the amount of heat generated around each of the lower electrodes will vary, even when the same voltage is applied to each of the phase change memory cells. These different amounts of heat will lead to differences in the respective resistances of corresponding phase change layers. Accordingly, phase change memory cells programmed to the same state may have different resistances.
The resistances of phase change memory cells (or in other words, the resistance of the corresponding phase change materials) within a phase change memory device typically exhibit bell shaped distributions. As a result, a state of a phase change memory cell is typically determined by comparing the resistance of the phase change memory cell with a reference read resistance between the distributions corresponding to the crystalline state and the amorphous state. To properly distinguish between the crystalline and amorphous states, the reference read resistance is located within a read margin between a minimum value of the distribution corresponding to the amorphous state and a maximum value of the distribution corresponding to the crystalline state.
Unfortunately, the distributions corresponding to the crystalline and amorphous states may be so close to each other that the read margin may be undesirably small. Where the read margin of the phase change memory cells is undesirably small, the reliability of the phase change memory device tends to be degraded because smaller read margins make it increasingly difficult for the reference read resistance to distinguish between the crystalline and amorphous states.
Of further note, the resistance of a phase change material may be varied as an external (ambient or operating) temperature changes. For example, assuming a set resistance of about 6 kΩ at 25° C. and a reset resistance of about 150 kΩ at 25° C., it is not uncommon for the set resistance to fall from about 6 kΩ to 3.45 kΩ and the reset resistance to fall from about 150 kΩ to 50 kΩ as the temperature rises from 25° C. to 85° C. Since this temperature variation in the reset resistance is more than the variation in the set resistance, a loss of read margin may arise between the set resistance and the reset resistance. This makes it increasingly difficult to distinguish between the set state and reset state at an associated sense amplifier. That is, if the reset resistance is much reduced, the prevalence of read errors will rise where a reset state must be discriminated form a set state.